General description
The 74LVC1G18 is a 1-of-2 non-inverting demultiplexer with a 3-state output. The device
buffers the data on input pin A and passes it either to output 1Y or 2Y, depending on
whether the state of the select input (pin S) is LOW or HIGH. Input can be driven from
either 3.3 or 5 V devices. These features allow the use of these devices in a mixed
3.3 and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
Features and benefits
 Wide supply voltage range from 1.65 to 5.5 V
 5 V tolerant input/output for interfacing with 5 V logic
 High noise immunity
 Complies with JEDEC standard:
 JESD8-7 (1.65 V to 1.95 V)
 JESD8-5 (2.3 V to 2.7 V)
 JESD8B/JESD36 (2.7 V to 3.6 V)
 ESD protection:
 HBM EIA/JESD22-A114E exceeds 2000 V
 MM EIA/JESD22-A115-A exceeds 200 V.
 24 mA output drive (VCC = 3.0 V)
 CMOS low power consumption
 Latch-up performance exceeds 250 mA
 Direct interface with TTL levels
 SOT363 and SOT457 package
 Specified from 40 to +85 C and 40 to +125 C.