Overview

M2 is designed to provide absolute top performance for a wide spectrum of teletext and graphic applications in standard and high end TV-sets and VCRs. M2 contains a data caption unit, a display unit and a high performance Infineon C16x based microcontroller (so that M2 becomes a one chip TV-controller) an up to level 3.5 teletext decoder and display processor with enhanced graphic accelerator capabilities. It is not only optimized for teletext usage but also, due to its extremely efficient architecture, can be used as a universal graphic engine.

Features

General

• Level 1.5, 2.5, 3.5 WST Display Compatible

• Fast External Bus Interface for SDRAM (Up to 8 MByte) and ROM or Flash-ROM (Up to 4 MByte)

• Embedded General Purpose 16 Bit CPU (Also used as TV-System Controller, C16x Compatible)

• Display Generation Based on Pixel Memory

• Program Code also Executable From External SDRAM

• Embedded Refresh Controller for External SDRAM

• Enhanced Programmable Low Power Modes

• Single 6 MHz Crystal Oscillator

• Multinorm H/V-Display Synchronization in Master or Slave Mode

• Free Programmable Pixel Clock from 10 MHz to 50 MHz

• Pixel Clock Independent from CPU Clock

•3×6 Bits RGB-DACs On-Chip

• Supply Voltage 2.5 and 3.3 V

• P-MQFP-128 Package



Microcontroller Features

• 16-bit C166-CPU Kernel (C16x Compatible)

• 60 ns Instruction Cycle Time

• 2 KBytes Dual Ported IRAM

• 2 KBytes XRAM On-chip

• General Purpose Timer Units (GPT1 and GPT2).

• Asynchronous/Synchronous Serial Interface (ASC0) with IrDA Support. Full-duplex

  Asynchronous Up To 2 MBaud or Half-duplex Synchronous up to 4.1 MBaud.

• High-speed Synchronous Serial Interface (SSC). Full- and Half-duplex synchronous up to 16.5 Mbaud

• 3 Independent, HW-supported Multi Master/Slave I2C Channels at 400 Kbit/s

• 16-Bit Watchdog Timer (WDT)

• Real Time Clock (RTC)

• On Chip Debug Support (OCDS)

• 4-Channel 8-bit A/D Converter

• 42 Multiple Purpose Ports

• 8 External Interrupts

• 33 Interrupt Nodes

Display Features

• OSD size from 0 to 2046 (0 to 1023) pixels in horizontal (vertical) direction

• Frame Buffer Based Display

• 2 HW Display Layers

• Support of Double Page Level 2.5 TTX in 100 Hz Systems

• Support of Transparency for both Layers Pixel by Pixel

• User Programmable Pixel Frequency from 10.0 MHz to 50 MHz

• Up to 65536 Displayable Colors in one Frame

• DMA Functionality

• Graphic Accelerator Functions (Draw Lines, Draw and Fill Rectangle, etc.)

• 1, 2, 4 or 8-bit Bitmaps (up to 256 out of 4096 colors)

• 12 bit/16 bit RGB Mode for Display of up to 65535 Colors

• HW-support for Proportional Characters

• HW-support for Italic Characters

• User Definable Character Fonts

• Fast Blanking and Contrast Reduction Output

Acquisition Features

• Two Independent Data Slicers (One Multistandard Slicer + one WSS-only Slicer)

• Parallel Multi-norm Slicing (TTX, VPS, WSS, CC, G+)

• Four Different Framing Codes Available

• Data Caption only Limited by available Memory

• Programmable VBI-buffer

• Full Channel Data Slicing Supported

• Fully Digital Signal Processing

• Noise Measurement and Controlled Noise Compensation

• Attenuation Measurement and Compensation

• Group Delay Measurement and Compensation

• Exact Decoding of Echo Disturbed Signals