PRODUCT OVERVIEW

FEATURES

♦ Memory configuration

   OTP ROM size: 6K * 16 bits.

   RAM size: 128 * 8 bits.

   Eight levels stack buffer

♦ I/O pin configuration

   Bi-directional: P0, P1, P2, P4, P5

   Input only: P4.7 shared with reset pin.

   Programmable open-drain: P1.0, P1.1

   Wakeup: P0, P1 level change trigger

   Pull-up resisters: P0, P1, P2, P4, P5

   External Interrupt trigger edge:

      P0.0 controlled by PEDGE register

      P0.1 is falling edge trigger only

♦ Powerful instructions

   One clocks per instruction cycle (1T)

   Most of instructions are one cycle only.

   All ROM area JMP instruction.

   All ROM area CALL address instruction.

   All ROM area lookup table function (MOVC)

♦ Four interrupt sources

   Two internal interrupts: T0, TC1.

   Two external interrupts: INT0, INT1.

♦ Two 8-bit Timer/Counter

   T0: Basic timer

   TC1: Auto-reload timer/Counter/PWM1/Buzzer output

♦ On chip watchdog timer and clock source is internal low clock RC type (16KHz @3V, 32KHz @5V).

♦ Dual system clocks

   External high clock: RC type up to 10 MHz

   External high clock: Crystal type up to 16 MHz

   Internal low clock: RC type 16KHz(3V), 32KHz(5V)

♦ Operating modes

   Normal mode: Both high and low clock active

   Slow mode: Low clock only

   Sleep mode: Both high and low clock stop

   Green mode: Periodical wakeup by T0 timer

♦ Package (Chip form support)

   P-DIP 40 pins

   SSOP 48 pins