GENERAL DESCRIPTION
The AD9577 provides a multioutput clock generator function, along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. The PLLs have I2C programmable output frequencies and formats. The fractional-N PLL can support spread spectrum clocking for reduced EMI radiated peak power. Both PLLs can support frequency margining. Other applications with demanding phase noise and jitter requirements can benefit from this part.

FEATURES
   Fully integrated dual PLL/VCO cores
   1 integer-N and 1 fractional-N PLL
   Continuous frequency coverage from 11.2 MHz to 200 MHz
      Most frequencies from 200 MHz to 637.5 MHz available
   PLL1 phase jitter (12 kHz to 20 MHz): 460 fs rms typical
   PLL2 phase jitter (12 kHz to 20 MHz)
      Integer-N mode: 470 fs rms typical
      Fractional-N mode: 660 fs rms typical
   Input crystal or reference clock frequency
   Optional reference frequency divide-by-2
   I2C programmable output frequencies
   Up to 4 LVDS/LVPECL or up to 8 LVCMOS output clocks
   1 CMOS buffered reference clock output
   Spread spectrum: downspread [0, −0.5]%
   2 pin-controlled frequency maps: margining
   Integrated loop filters
   Space saving, 6 mm × 6 mm, 40-lead LFCSP package
   1.02 W power dissipation (LVDS operation)
   1.235 W power dissipation (LVPECL operation)
   3.3 V operation

APPLICATIONS
   Low jitter, low phase noise multioutput clock generator for
      data communications applications including Ethernet,
      Fibre Channel, SONET, SDH, PCI-e, SATA, PTN, OTN,
      ADC/DAC, and digital video
   Spread spectrum clocking