Description
The LCK4950 is a PLL-based clock driver device intended for high-performance clock tree designs. The LCK4950 is 3.3 V compatible with output frequencies of up to 180 MHz and output skews of 200 ps. The LCK4950 can accommodate the most demanding tree designs by employing a fully differential PLL design. This minimizes cycle-to-cycle jitter, which is critical when the device is acting as the reference clock for PLLs in today’s microprocessors and ASICs. The device has nine low-skew configurable outputs for support of the clocking needs of the various high-performance microprocessors.

Features
■ Fully integrated phase-locked loop (PLL)
■ Oscillator or crystal reference input
■ Output frequency up to 180 MHz
■ Outputs disable in high impedance
■ Compatible with PowerPC®, Intel®, and highperformance RISC microprocessors
■ TQFP packaging
■ Output frequency configurable
■ ±35 ps typical cycle-to-cycle jitter
■ Pin compatible with the Motorola® MPC950 clock driver