The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and thebistable will perform according to the truth table as long as minimum set-up andhold time are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.