Introduction
This document contains information for the 80960Jx microprocessor, including electrical characteristics and package pinout information. Detailed functional descriptions — other than parametric performance — are published in the i960® Jx Microprocessor Developer’s Manual (272483).

80960Jx Overview
The 80960Jx offers high performance to cost-sensitive 32-bit embedded applications. The 80960Jx is object code compatible with the 80960 Core Architecture and is capable of sustained execution at the rate of one instruction per clock. This processor’s features include generous instruction cache, data cache and data RAM. It also boasts a fast interrupt mechanism and dual-programmable timer units.

Product Features
■ Pin/Code Compatible with all 80960Jx Processors
■ High-Performance Embedded Architecture
    —One Instruction/Clock Execution
    —Core Clock Rate is:
        80960JA/JF 1x the Bus Clock
        80960JD 2x the Bus Clock
        80960JT 3x the Bus Clock
    —Load/Store Programming Model
    —Sixteen 32-Bit Global Registers
    —Sixteen 32-Bit Local Registers (8 sets)
    —Nine Addressing Modes
    —User/Supervisor Protection Model
■ Two-Way Set Associative Instruction Cache
    —80960JA - 2 Kbyte
    —80960JF/JD - 4 Kbyte
    —80960JT - 16 Kbyte
    —Programmable Cache-Locking Mechanism
■ Direct Mapped Data Cache
    —80960JA - 1 Kbyte
    —80960JF/JD - 2 Kbyte
    —80960JT - 4 Kbyte
    —Write Through Operation
■ On-Chip Stack Frame Cache
    —Seven Register Sets Can Be Saved
    —Automatic Allocation on Call/Return
    —0-7 Frames Reserved for High-Priority Interrupts
■ On-Chip Data RAM
    —1 Kbyte Critical Variable Storage
    —Single-Cycle Access
■ 3.3 V Supply Voltage
    —5 V Tolerant Inputs
    —TTL Compatible Outputs
■ High Bandwidth Burst Bus
    —32-Bit Multiplexed Address/Data
    —Programmable Memory Configuration
    —Selectable 8-, 16-, 32-Bit Bus Widths
    —Supports Unaligned Accesses
    —Big or Little Endian Byte Ordering
■ High-Speed Interrupt Controller
    —31 Programmable Priorities
    —Eight Maskable Pins plus NMI
    —Up to 240 Vectors in Expanded Mode
■ Two On-Chip Timers
    —Independent 32-Bit Counting
    —Clock Prescaling by 1, 2, 4 or 8
    —lnternal Interrupt Sources
■ Halt Mode for Low Power
■ IEEE 1149.1 (JTAG) Boundary Scan Compatibility
■ Packages
    —132-Lead Pin Grid Array (PGA)
    —132-Lead Plastic Quad Flat Pack (PQFP)
    —196-Ball Mini Plastic Ball Grid Array (MPBGA)