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AD9260ASRL 데이터시트(PDF) 14 Page - Analog Devices

부품명 AD9260ASRL
상세설명  High Speed Oversampling CMOS ADC
PDF  45 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
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AD9260ASRL 데이터시트(HTML) 14 Page - Analog Devices

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AD9260
Rev. C | Page 13 of 44
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AD9260
12
13
14
15
16
17
18
19
2 0
21
22
3
4
5
6
7
1
2
10
11
8
9
40
39
38
41
42
43
44
36
35
34
37
29
30
31
32
27
28
25
26
23
24
33 REFCOM
VREF
SENSE
RESET
AVSS
AVDD
CS
DVSS
AVSS
DVDD
AVDD
DRVSS
DRVDD
CLK
READ
(LSB) BIT16
BIT15
BIT14
DAV
OTR
BIT1 (MSB)
BIT2
NC = NO CONNECT
Figure 10. Pin Configuration
Table 11. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
DVSS
Digital Ground.
2, 29, 38
AVSS
Analog Ground.
3
DVDD
+3 V to +5 V Digital Supply.
4, 28, 44
AVDD
+5 V Analog Supply.
5
DRVSS
Digital Output Driver Ground.
6
DRVDD
+3 V to +5 V Digital Output Driver Supply.
7
CLK
Clock Input.
8
READ
Part of DSP Interface—Pull Low to Disable Output Bits.
9
BIT16
Least Significant Data Bit (LSB).
10–23
BIT15–BIT2
Data Output Bit.
24
BIT1
Most Significant Data Bit (MSB).
25
OTR
Out of Range—Set When Converter or Filter Overflows.
26
DAV
Data Available.
27
CS
Chip Select (CS): Active LOW.
30
RESET
RESET: Active LOW.
31
SENSE
Reference Amplifier SENSE: Selects REF Level.
32
VREF
Input Span Select Reference I/O.
33
REFCOM
Reference Common.
34
MODE
Mode Select—Selects Decimation Mode.
35
BIAS
Power Bias.
36
CAPB
Noise Reduction Pin—Decouples Reference Level.
37
CAPT
Noise Reduction Pin—Decouples Reference Level.
39
CML
Common-Mode Level (AVDD/2.5).
40, 43
NC
No Connect (Ground for Shielding Purposes).
41
VINA
Analog Input Pin (+).
42
VINB
Analog Input Pin (–).



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