ST72F324J2T6 datasheet(133/156 Pages) STMICROELECTRONICS

부품명	ST72F324J2T6

상세설명	8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE

PDF	156 Pages

Scroll/Zoom	100%

제조업체	STMICROELECTRONICS [STMicroelectronics]

홈페이지	http://www.st.com

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ST72324J/K

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EMC CHARACTERISTICS (Cont’d)

True Open Drain Pin Protection

The centralized protection (4) is not involved in the

discharge of the ESD stresses applied to true

open drain pads due to the fact that a P-Buffer and

diode to VDD are not implemented. An additional

local protection between the pad and VSS (5a &

5b) is implemented to completely absorb the posi-

tive ESD discharge.

Multisupply Configuration

When several types of ground (VSS, VSSA, ...) and

power supply (VDD, VAREF, ...) are available for

any reason (better noise immunity...), the structure

shown in Figure 79 is implemented to protect the

device against ESD.

Figure 77. Positive Stress on a True Open Drain Pad vs. VSS

Figure 78. Negative Stress on a True Open Drain Pad vs. VDD

Figure 79. Multisupply Configuration

VDD

VSS

(1)

(2b)

(4)

OUT

VDD

VSS

(3b)

Main path

Path to avoid

(5a)

(5b)

VDD

VSS

(1)

(2b)

(4)

OUT

VDD

VSS

(3b)

Main path

(3b)

VAREF

VSSA

VAREF

VDD

VSS

BACK TO BACK DIODE

BETWEEN GROUNDS

VSSA

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