ST72F324J2T6 datasheet(134/156 Pages) STMICROELECTRONICS

134 / 156 page

ST72324J/K

134/156

12.8 I/O PORT PIN CHARACTERISTICS

12.8.1 General Characteristics

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Figure 80. Connecting Unused I/O Pins

Figure 81. Typical IPU vs. VDD with VIN=VSS

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

3. When the current limitation is not possible, the VIN maximum must be respected, otherwise refer to IINJ(PIN) specifica-

tion. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. Refer to Section 12.2.2

on page 113 for more details.

4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for

example or an external pull-up or pull-down resistor (see Figure 80). Data based on design simulation and/or technology

characteristics, not tested in production.

5. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics de-

scribed in Figure 81).

6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external

interrupt source.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage 1)

CMOS ports

0.3xVDD

VIH

Input high level voltage 1)

0.7xVDD

Vhys

Schmitt trigger voltage hysteresis 2)

0.7

VIL

Input low level voltage 1)

TTL ports

0.8

VIH

Input high level voltage 1)

Vhys

Schmitt trigger voltage hysteresis 2)

IINJ(PIN)

Injected Current on an I/O pin

VDD=5V

± 4

ΣI

INJ(PIN)

3) Total injected current (sum of all I/O

and control pins)

± 25

Input leakage current

VSS≤VIN≤VDD

±1

µA

Static current consumption

Floating input mode4)

200

RPU

Weak pull-up equivalent resistor 5)

VIN=VSS

VDD=5V

120

250

Ω

CIO

I/O pin capacitance

tf(IO)out

Output high to low level fall time 1)

CL=50pF

Between 10% and 90%

tr(IO)out

Output low to high level rise time 1)

tw(IT)in

External interrupt pulse time 6)

1tCPU

10k

Ω

UNUSED I/O PORT

ST72XXX

10k

Ω

UNUSED I/O PORT

ST72XXX

VDD

22.5

33 .5

4.5

55.5

Vdd (V)

Ta=1 40°C

Ta=9 5°C

Ta=2 5°C

Ta=-45 °C

ST72F324J2T6 데이터시트(PDF) 134 Page - STMicroelectronics

ST72F324J2T6 데이터시트(HTML) 134 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL