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TDA7333

7

Functional Description

7.1 Overview

The new RDS/RBDS processor contains all RDS/RBDS relevant functions on a single chip. It recovers the

inaudible RDS/RBDS information which are transmitted on most FM radio broadcasting stations.

Due to an integrated 3rd order sigma delta converter, which samples the MPX signal, all further processing

is done in the digital domain and therefore very economical. After filtering the highly oversampled output

of the A/D converter, the RDS/RBDS demodulator extracts the RDS DataClock , RDS Data Signal and

the Quality information. A next RDS/RBDS decoder will synchronize the bitwise RDS stream to a group

and block wise information. This processing includes an error detection and error correction algorithm. In

addition, an automatic flywheel control avoids exhaustive data exchange between the RDS/RBDS proces-

sor and the host.

The device operates in accordance with the EBU (European Broadcasting Union) specifications.

7.2 Sigma Delta Converter

The Sigma Delta Modulator is a 3rd order (second order-first order cascade) structure. Therefore a multibit out-

put (2 bit streams) represents the analog input signal. A next digital noise canceller will take the 2 bit streams

and calculates a combined stream which is then fed to the decimation filter. The modulator works at a sampling

frequency of XTI/2. The oversampling factor in relation to the band of interest (57 kHz +- 2.4 kHz) is 38.

7.3 Sinc4/16 Decimation Filter

The oversampled data delivered from the modulator are decimated by a value of 16 with a 4th order Sinc Filter.

This is considered to be the optimum solution for high decimation factors and for a 3rd order sigma delta mod-

ulator.

Symbol

Parameter

Test Conditions

Values

Unit

Min.

Typ.

Max.

Passband Ripple

-0.5

+0.5

dB

Stopband Corner Frequencies

53.0

61

kHz

Stopband Attenuation

-43

dB

Interpolation Factor

32

400

kHz

SPI

clock frequency in SPI mode

1

MHz

clock high time

450

ns

clock low time

450

ns

chip select setup time

500

ns

chip select hold

500

ns

output data valid

250

ns

output hold

0

ns

deselect time

1000

ns

data setup time

200

ns

data hold time

200

ns

Table 6. Electrical Characteristics (continued)