CS4103 datasheet(21/24 Pages) NSC

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Electrical Characteristics (Continued)

4.4

AC SPECIFICATIONS

Figure 4-1. SCLK to Data Valid Timing Waveform

Figure 4-2. Setup and Hold Timing Waveform

Figure 4-3. Rise and Fall Timing Waveforms

Table 4-4. IEEE-1394A PHY-Link Interface Timings

Symbol

Parameter

Min

Typ

Max

Unit

Conditions

SCLK Frequency

49.152MHz +/-100ppm

MHz

SCLK Duty Cycle

tPD1

Delay Time, SCLK High to Initial Instance of

DATA[0:7] and CTRL[0:1] Valid

0.5

13.5

tPD2

Delay Time, SCLK High to Subsequent

Instances of DATA[0:7] and CTRL[0:1] Valid

0.5

13.5

tPD3

Delay Time, SCLK High to DATA[0:7] and

CTRL[0:1] Invalid

0.5

13.5

tPSU

Setup Time, DATA[0:7], CTRL[0:1], and

LREQ before SCLK High

6ns

tPH

Hold Time, DATA[0:7], CTRL[0:1], and

LREQ after SCLK High

0ns

Rise Time, DATA[0:7], CTRL[0:1], and SCLK

0.7

2.4

Fall Time, DATA[0:7], CTRL[0:1], and SCLK

0.7

2.4

SCLK

DATA[0:7],

tPD1

CTRL[0:1]

tPD2

tPD3

50%

tCLK

SCLK

tPSU

tPH

50%

DATA[0:7],

CTRL[0:1]

90%

DATA[0:7],

CTRL[0:1],

10%

90%

10%

SCLK

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