SLG46170 datasheet(17/87 Pages) DIALOG

17 / 87 page

000-0046170-103

Page 16 of 86

SLG46170

6.0 Summary of Macrocell Function

6.1 I/O Pins

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Digital Input (low voltage or normal voltage, with or without Schmitt Trigger)

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Open Drain Outputs

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Push Pull Outputs

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10 k

/100 k/1 Mpull-up/pull-down resistors

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40 mA Open Drain 4X Drive output

6.2 Connection Matrix

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Digital matrix for circuit connections based on user design

6.3 Combinational Logic Look Up Tables (LUTs – 15 total)

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Five 2-bit Lookup Tables

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Nine 3-bit Lookup Tables

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One 4-bit Lookup Tables

6.4 Combination Function Macrocell (2 total)

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One Selectable FF/Latch or 2-bit LUT

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One Selectable Pipe Delay or 3-bit LUT

6.5 Delays/Counters (8 total)

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Two 14-bit delay/counters: Range 1-16384 clock cycles

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Four 8-bit delays/counters: Range 1-255 clock cycles

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Two 8-bit delays/counters with external clock/reset: Range 1-255 clock cycles

6.6 Digital Storage Elements (6 total)

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Six D Flip-Flops or Latches

6.7 Pipe Delay (Part of Combination Function Macrocell)

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16 stage / 3 output

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One 1 stage fixed output

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Two 1-16 stage selectable outputs.

6.8 Programmable Delay

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150 ns/300 ns/450 ns /600 ns @ 3.3 V

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Includes Edge Detection function

6.9 Additional Logic Functions (2 total)

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Two Deglitch filter macrocells

6.10 RC Oscillator

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25 kHz and 2 MHz selectable frequency

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First stage divider (4): OSC/1, OSC/2, OSC/4, and OSC/8

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Second stage divider (5): OSC/1, OSC/4, selectable (OSC/8, OSC/12, OSC/24, or OSC/64), OSC/3, and additional OSC/3

(from selectable output)

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