SLG46536 datasheet(92/165 Pages) DIALOG

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SLG46536_DS_105

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SLG46536

Each of the ACMP cells has a positive input signal that can be provided by a variety of external sources. There is also a selectable

gain stage (1X, 0.5X, 0.33X, 0.25X) before connection to the analog comparator. The Gain divider is unbuffered and consists of

250 KΩ (typ.) resistors, see Table 80. For gain divider accuracy refer to Table 81. IN- voltage range: 0 - 1.2 V. Can use Vref

selection VDD/4 and VDD/3 to maintain this input range.

Input bias current < 1 nA (typ).

Each cell also has a hysteresis selection, to offer hysteresis of 0 mV, 25 mV, 50 mV or 200 mV. The 50 mV and 200 mV hysteresis

options can be used with internal voltage reference only, while 25 mV hysteresis option can be used with both internal and external

voltage reference. The 50 mV and 200 mV hysteresis options are one way hysteresis. It means that the actual thresholds will be

Vref (high threshold) and Vref - hysteresis (low threshold). The ACMP output will retain its previous value, if the input voltage is

within threshold window (between Vref and Vref - hysteresis). Please note: for the 25 mV hysteresis option threshold levels will

be Vref + hysteresis/2 (high threshold) and Vref – hysteresis/2 (low threshold).

Note: Any ACMP powered on enables the BandGap internal circuit as well. An analog voltage will appear on Vref even when the

Force BandGap option is set as Disabled.

Table 80. Gain Divider Input Resistance

Gain

x0.5

x0.33

x0.25

Input Resistance

100 MΩ

1 MΩ

0.75 MΩ

1 MΩ

Table 81. Gain Divider Accuracy

Gain

x0.5

x0.33

x0.25

Accuracy

±0.51%

±0.34%

±0.25%

Figure 51. Maximum Power On Delay vs. VDD,

BG = 550 µs.

600

650

700

750

800

850

900

950

1000

1050

1100

VDD (V)

-40⁰C

+25⁰C

+85⁰C

Figure 52. Maximum Power On Delay vs. VDD,

BG = 100 µs.

120

130

140

150

160

170

180

190

200

210

220

VDD (V)

-40⁰C

+25⁰C

+85⁰C

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