ISP1181B datasheet(13/70 Pages) PHILIPS

13 / 70 page

Philips Semiconductors

ISP1181B

Full-speed USB peripheral controller

Product data

Rev. 02 — 07 December 2004

13 of 70

9397 750 13958

Each programmable FIFO can be conﬁgured independently via its ECR, but the total

physical size of all enabled endpoints (IN plus OUT) must not exceed 2462 bytes.

Table 6 shows an example of a conﬁguration ﬁtting in the maximum available space of

2462 bytes. The total number of logical bytes in the example is 1311. The physical

storage capacity used for double buffering is managed by the peripheral hardware

and is transparent to the user.

Table 5:

Programmable FIFO size

FFOSZ[3:0]

Non-isochronous

Isochronous

0000

8 bytes

16 bytes

0001

16 bytes

32 bytes

0010

32 bytes

48 bytes

0011

64 bytes

0100

reserved

96 bytes

0101

reserved

128 bytes

0110

reserved

160 bytes

0111

reserved

192 bytes

1000

reserved

256 bytes

1001

reserved

320 bytes

1010

reserved

384 bytes

1011

reserved

512 bytes

1100

reserved

640 bytes

1101

reserved

768 bytes

1110

reserved

896 bytes

1111

reserved

1023 bytes

Table 6:

Memory conﬁguration example

Physical size

(bytes)

Logical size

(bytes)

Endpoint description

control IN (64 byte ﬁxed)

control OUT (64 byte ﬁxed)

2046

1023

double-buffered 1023-byte isochronous endpoint

16-byte interrupt OUT

16-byte interrupt IN

128

double-buffered 64-byte bulk OUT

128

double-buffered 64-byte bulk IN

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