전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

AD8452 데이터시트(PDF) 17 Page - Analog Devices

부품명 AD8452
상세설명  Precision Integrated Analog Front End, Controller
PDF  35 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD8452 데이터시트(HTML) 17 Page - Analog Devices

Back Button AD8452 Datasheet HTML 13Page - Analog Devices AD8452 Datasheet HTML 14Page - Analog Devices AD8452 Datasheet HTML 15Page - Analog Devices AD8452 Datasheet HTML 16Page - Analog Devices AD8452 Datasheet HTML 17Page - Analog Devices AD8452 Datasheet HTML 18Page - Analog Devices AD8452 Datasheet HTML 19Page - Analog Devices AD8452 Datasheet HTML 20Page - Analog Devices AD8452 Datasheet HTML 21Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 17 / 35 page
background image
AD8452
Data Sheet
Rev. 0 | Page 16 of 34
PULSE-WIDTH MODULATOR
TEMPERATURE (°C)
30
20
40
50
60
70
80
90
0
–10
10
–20
–30
–40
5.10
VIN = 6V
VIN = 24V
VIN = 60V
5.08
5.06
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
Figure 22. SS Pin Current vs. Temperature
CH1 5.00V 1MΩ
20.0M
1MΩ
20.0M
1MΩ
20.0M
1MΩ
20.0M
20µs/DIV
CH1
3.1V
CH3 5.00V
CH2 5.00V
CH4 5.00V
1
2
4
EN
DH
DL
SYNC
B
W
B
W
B
W
B
W
Figure 23. Timing, Referred to Startup (0 V to 5 V at EN Pin), As Observed
at Three Logic Output Pins When AD8452 Is in Charge Mode
1
2
3
4
CSS = 0.1µF
MODE = 5V
CH1 5.00V 1MΩ
20.0M
1MΩ
20.0M
1MΩ
20.0M
1MΩ
20.0M 20ms/DIV
CH1
2.3V
CH3 5.00V
CH2 2.00V
CH4 5.00V
EN
DH
DL
SS
B
W
B
W
B
W
B
W
Figure 24. Soft Start Ramp Timing at SS Pin, Referred to Startup (0 V to 5 V
at the EN Pin) As Observed at Logic Level Outputs, DH and DL,
When AD8452 Is in Charge Mode
1
2
3
4
EN
SS
DH
DL
CSS = 0.1µF
MODE = 0V
CH1 5.00V 1MΩ
20.0M
1MΩ
20.0M
1MΩ
20.0M
1MΩ
20.0M 20ms/DIV
CH1
2.3V
CH3 5.00V
CH2 5.00V
CH4 5.00V
B
W
B
W
B
W
B
W
Figure 25. Shows Reversal of DH Pin and DL Pin Timing at Startup
(0 V to 5 V at EN Pin) When AD8452 Is in Discharge Mode
210
30
70
110
150
190
50
90
130
170
50
150
100
200
250
300
fSET (kHz)
Figure 26. RFREQ (MASTER) vs. Switching Frequency (fSET)
0
1.5
3.0
4.5
6.0
7.5
9.0
500
450
400
350
300
250
200
150
100
50
0
PHASE DELAY (µs)
Figure 27. RSCFG (Calculated) vs. Phase Time Delay (tDELAY)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com