64-Channel, 24-Bit Current-to-Digital ADC

ADAS1127

Rev. SpA

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FEATURES

64-channel, low level current-to-digital converter

Up to 24-bit resolution

Up to 19.7 kSPS (50.7 µs integration time)

Simultaneous sampling

User-adjustable full-scale range

INL: ±0.025% of reading ±0.75 ppm of FSR

Very low power dissipation: 6.25 mW/channel

LVDS self-clocked serial data interface

SPI configuration registers (daisy-chain)

On-board temperature sensor and reference buffer

10 mm × 10 mm, mini-BGA package

Low cost external components

Support tools

Evaluation board

Reference design with reference layout

FPGA Verilog code

APPLICATIONS

Medical, industrial, and security CT scanner data acquisition

Photodiode sensors

Dosimetry and radiation therapy systems

Optical fiber power monitoring

X-ray detection systems

High channel-count data acquisition systems (current or

voltage inputs)

GENERAL DESCRIPTION

The ADAS1127 is a 64-channel, current-to-digital, analog-to-

digital converter (ADC). It contains 64 low power, low noise,

low input current integrators, simultaneous sample-and-holds,

and a high speed, high resolution ADCs with configurable

sampling rate and resolutions up to 24 bits.

All converted channel results are output on a single LVDS self-

clocked serial interface, which reduces external hardware.

An SPI-compatible serial interface allows configuration of the

ADC using the SDI input. The SDO output allows the user to

daisy-chain several ADCs on a single, 3-wire bus. The

ADAS1127 uses the separate supply IOVDD to reduce the

digital noise effect on the conversions.

The ADAS1127 is in a 10 mm × 10 mm, mini-BGA package.

FUNCTIONAL BLOCK DIAGRAM

F

S/H

OR0

F

S/H

OR31

AN0

AN31

F

S/H

OR32

F

S/H

OR63

AN32

AN63

KGND

ADCL

+

–

DATA

PROCESSING

LVDS/CMOS

INTERFACE

TEMPERATURE

OR[0:63]

ADAS1127

2.5V

3.3V

TO NEXT

SDI

SDI

SDO

BUFP

BUFN

REF

2.048V

SDI

FROM

PREVIOUS

SDO

SDI

CONFIGURATION

SCK

CS

DOUTx

CLKx

SYNC

IOVDD

RESET

IOGND

TO ALL ADCs

2.5V

FROM DOUT

OF OTHER ADCs

FPGA

VIO

Figure 1.