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ST25DV04K 데이터시트(PDF) 94 Page - STMicroelectronics

부품명 ST25DV04K
상세설명  Dynamic NFC/RFID tag IC with 4-Kbit, 16-Kbit or 64-Kbit EEPROM,and fast transfer mode capability
PDF  220 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST25DV04K 데이터시트(HTML) 94 Page - STMicroelectronics

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I2C operation
ST25DV04K ST25DV16K ST25DV64K
94/220
DocID027603 Rev 4
6.5
I2C read operations
Read operation in user memory is performed successfully only if:
Area to which the byte belongs is not read protected by I2CSS register.
Area to which the byte belongs is read protected by I2CSS register, but I2C security
session is open.
Read operations in system memory and dynamic registers are done independently of any
protection mechanism, except I2C_PWD register which needs I2C security session to be
open first.
Read operation in fast transfer mode’s mailbox is performed successfully only if fast transfer
mode is activated.
If read is not successful, ST25DVxxx releases the bus and I2C host reads byte value FFh.
After the successful completion of a read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
After an unsuccessful read operation, ST25DVxxx enters in I2C dead state: internal address
counter is not incremented, and ST25DVxxx is waiting for a full new I2C instruction.
6.5.1
Random Address Read
A dummy write is first performed to load the address into this address counter (as shown in
Figure 29: Read mode sequences) but without sending a Stop condition. Then, the bus
master sends another Start condition, and repeats the device select code, with the
Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the contents of the
addressed byte. The bus master must not acknowledge the byte, and terminates the
transfer with a Stop condition.
6.5.2
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges
this, and outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 29: Read mode sequences, without acknowledging the byte.



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