ST25DV16K datasheet(90/220 Pages) STMICROELECTRONICS

90 / 220 page

I2C operation

ST25DV04K ST25DV16K ST25DV64K

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DocID027603 Rev 4

6.4.1

I2C Byte write

After the device select code and the address bytes, the bus master sends one data byte.

If byte write is not inhibited, the device replies with Ack.

If byte write is inhibited, the device replies with NoAck.

The bus master terminates the transfer by generating a Stop condition (see Figure 26: Write

mode sequences when write is not inhibited).

For byte write in EEPROM (user memory or system configuration), internal programming

starts after the Ack, for a duration of tW (as defined in Table 209: I2C AC characteristics up

to 85°C and Table 210: I2C AC characteristics up to 125°C).

For writes in fast transfer mode buffer or Dynamic registers, internal programming is done at

the Ack.

If byte write is inhibited, the device replies with NoAck. The bus master terminates the

transfer by generating a Stop condition and byte location not is modified (see Figure 27:

Write mode sequences when write is inhibited).

Byte write is inhibited if byte complies with one of the following conditions:

•

Byte is in user memory and is write protected with LOCK_CCFILE register.

•

Byte is in user memory and is write protected with I2CSS register, and I2C security

session is closed.

•

Byte is in user memory and fast transfer mode is activated.

•

Byte is in system memory and is a Read Only register.

•

Byte is in system memory and I2C security session is closed.

•

Byte is in fast transfer mode’s mailbox and is not the first Byte of mailbox.

•

Byte is in fast transfer mode’s mailbox and mailbox is busy.

•

Byte is in fast transfer mode’s mailbox and fast transfer mode is not activated.

•

Byte is in dynamic registers area and is a Read Only register.

6.4.2

I2C Sequential write

The I2C sequential write allows up to 256 bytes to be written in one command, provided they

are all located in the same user memory area or are all located in writable addresses.

After each byte is transferred, the internal byte address counter is incremented.

For each byte sent by the bus master:

•

If byte write is not inhibited, the device replies with Ack.

•

If byte write is inhibited, the device replies with NoAck.

The transfer is terminated by the bus master generating a Stop condition:

•

For writes in EEPROM (user memory or system configuration), if all bytes have been

Ack'ed, internal programming of all bytes starts after the last Ack, for a duration

dependent on the number of bytes to write (see below).

•

For writes in fast transfer mode buffer or Dynamic registers, if all bytes have been

Ack'ed, internal programming is done at the Ack.

•

If some bytes have been NotAck’ed, no internal programming is done (0 byte written).

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