AD9671EBZ datasheet(48/61 Pages) AD

48 / 61 page

Data Sheet

AD9671

Rev. A| Page 47 of 60

Address

Value

Description

0x150

0x03

JESD204B scrambler disabled and four-lane configuration (L = 4)

0x182

0x82

Autoconfigures PLL

0x181

0x02

PLL N divider = ÷20

0x186

0xAA

Disable continuous data resync (continuous data resync is not recommended during real-time

scanning; one-time data resync is sufficient)

0x10C3

0x20

Set SPI TX_TRIG± and index profile

0x00F

0x18

Set low-pass filter cutoff frequency, bandwidth mode

0x02B

0x40

Set analog LPF and HPF to defaults, tune filters4

1 Setting the profile index requires an additional SPI write in SPI MSB mode before the chip is run to complete the current profile buffer update.

2 Running the chip from full power-down mode requires 375 μs wake-up time as listed in Table 3.

3 The software TX_TRIG trigger switches the demodulator/decimator digital block to a running state. It may not be needed if hardware the TX_TRIX signal is used to run

the digital block.

4 Tuning the filters requires 512 ADC clock cycles.

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