LTC4002-4.2

13

400242i

APPLICATIO S I FOR ATIO

Next, choose the P-channel MOSFET. The Si6435ADQ in

(max) offers a small solution. The maximum power dissi-

temperature is:

P

AmV

V

W

()

Ω

()( )

=

1 5

55

4

5

0 099

2

.

.

85

°C. The output capacitor is chosen for an ESR similar to

the battery impedance of about 100m

Ω. The ripple voltage

on the BAT pin is:

V

I

ESR

A

mV

OUT RIPPLE

LMAX

()

()

..

=

∆

()

Ω

()

=

2

098

0 1

2

49

C1: Taiyo Yuden TMK325BJ106MM

C2: Taiyo Yuden JMK325BJ226MM

L1: TOKO B952AS-6R8N

The Schottky diode D2 shown in Figure 1 conducts current

when the pass transistor is off. In a low duty cycle case, the

current rating should be the same or higher than the

charge current. Also it should withstand reverse voltage as

Board Layout Suggestions

When laying out the printed circuit board, the following

considerations should be taken to ensure proper opera-

tion of the LTC4002-4.2.

GATE pin rise and fall times are 20ns and 50ns respectively

diode, pass transistor and the input bypass capacitor

traces should be kept as short as possible. The positive

side of the input capacitor should be close to the source of

the P-channel MOSFET; it provides the AC current to the

pass transistor. The connection between the catch diode

and the pass transistor should also be kept as short as

possible. The SENSE and BAT pins should be connected

directly to the sense resistor (Kelvin sensing) for best

charge current accuracy.

The compensation capacitor connected at the COMP pin

should return to the ground pin of the IC or as close to it

as possible. This will prevent ground noise from disrupt-

ing the loop stability. The ground pin also works as a heat

sink, therefore use a generous amount of copper around

and/or high gate capacitance applications.