ATPL250A datasheet(4/28 Pages) ATMEL

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ATPL250A [DATASHEET]

Atmel-43079F-ATPL250A-Datasheet_22-Sep-16

Signal Description

Table 3-1.

Signal Description List

Signal Name

Function

Type

Active

Level

Voltage

reference

Comments

Power Supplies

VDDIO

3.3V digital supply. Digital power supply must be

decoupled by external capacitors

Power

3.0V to 3.6V

VDDIN

3.3V Digital LDO input supply

Power

3.0V to 3.6V

VDDIN AN

3.3V Analog LDO input supply

Power

3.0V to 3.6V

VDDOUT AN

1.2V Analog LDO output. A capacitor in the range

0.1 μF - 10 μF must be connected to each pin

Power

1.2V

VDDOUT

1.2V Digital LDO output. A capacitor in the range

0.1 μF - 10 μF must be connected to each pin

Power

1.2V

VDDPLL

1.2V PLL supply. It must be decoupled by a 100nF

external capacitor, and connected to VDDOUT

through a filter (Cut off frequency: 25 kHz)

Power

1.2V

GND(1)

Digital Ground

Power

AGND(1)

Analog Ground

Power

Clocks, Oscillators and PLLs

CLKEA(2)

External Clock Oscillator

• CLKEA must be connected to one terminal of a

crystal (when a crystal is being used) or used

as input for external clock signal

Input

VDDIO

CLKEB(2)

External Clock Oscillator

• CLKEB must be connected to one terminal of a

crystal (when a crystal is being used) or must

be floating when an external clock signal is

connected through CLKEA

I/O

VDDIO

CLKOUT

12 MHz CLK Output

Output

VDDIO

Reset/Test

ARST

Asynchronous Reset

Input

Low

VDDIO

Internal pull up(3)

SRST

Synchronous Reset

Input

Low

VDDIO

Internal pull up(3)

PLL INIT

PLL Initialization Signal

Input

Low

VDDIO

Internal pull up(3)

GPLC (G3 Power Line Communications) Transceiver

EMIT [0:11](4)

PLC Tri-state Transmission ports

Output

VDDIO

AGC [0:5]

Automatic Gain Control:

• These digital tri-state outputs are managed by

AGC hardware logic to drive external circuitry

when input signal attenuation is needed

Output

VDDIO

TXRX0

Analog Front-End Transmission/Reception for

TXDRV0

• This digital output is used to modify external

coupling behavior in Transmission/Reception.

The suitable value depends on the external

circuitry configuration. The polarity of this pin

can be inverted by software

Output

VDDIO

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