SSD1852Z datasheet(21/55 Pages) ETC

21 / 55 page

SSD1852

Rev 1.0

01/2003

SOLOMON

7.11 Display Data Latch

This block is a series of latches carrying the display signal information. These latches

hold the data, which will be fed to HV Buffer Cell and Level Selector to output the required

voltage levels. The number of latches are 128+129= 257

7.12 HV Buffer Cell (Level Shifter)

HV Buffer Cell works as a level shifter that translates the low voltage output signal to the

required driving voltage. The output is shifted out with an internal FRM clock that comes from

the Display Timing Generator. The voltage levels are given by the level selector which is

synchronized with the internal M signal.

7.13 Level Selector

Level Selector is a control of the display synchronization. Display voltage can be

separated into two sets and used with different cycles. Synchronization is important since it

selects the required LCD voltage level to the HV Buffer Cell, which in turn outputs the ROW or

SEG LCD waveform.

7.14 LCD Panel Driving Waveform

The following is an example of how the Common and Segment drivers may be connected

to a LCD panel. The waveforms are shown in Figure 8 illustrating the desired multiplex scheme

with N-line Inversion feature disabled (default).

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