XR88C92 datasheet(7/32 Pages) EXAR

7 / 32 page

XR88C92/192

Rev. 1.31

INTERNAL CONTROL LOGIC

The internal control logic of the XR88C92/192 receives

operation commands from the central processing unit

(CPU) and generates appropriate signals to the internal

sections to control device operation. The internal control

logic takes in the following inputs:

• -CS, which is the XR88C92/192 chip-select;

• -IOR (read) and -IOW (write), which allow data

transfers between the CPU and XR88C92/192

via the data bus (D0 to D7);

• four register-select lines (A0 through A3) which are

decoded to allow access to the registers within the

XR88C92/192;

• RESET (reset), which initializes or resets all

outputs and internal registers.

COMMUNICATION CHANNELS A AND B

Each communication channel includes a full-duplex

asynchronous receiver/transmitter (UART). The oper-

ating frequency for each receiver and each transmitter

can be selected independently from the baud rate

generator, the Counter/Timer (C/T), or from an external

clock. The transmitter accepts parallel data from the

CPU, converts it to a serial bit stream in the form of a

character and outputs it on the Transmit Data output pin

(TXA, TXB). The character consists of start, stop, and

optional parity bits, The receiver accepts serial data on

the Receive Data input pin (RXA, RXB), converts this

serial input to parallel format, checks for a start bit, stop

bit, parity bit (if any), framing error, overrun or break

condition, and transfers the data byte to the CPU during

read operations.

TIMING LOGIC

The timing logic consists of

• a crystal oscillator,

• a baud rate generator (BRG),

• clock selector logic, and

• a programmable 16-bit counter/timer (C/T).

The

crystal oscillator operates directly from a 3.6864

MHz crystal connected across the XTAL1 and XTAL2

inputs or from an external clock of the appropriate

frequency connected to XTAL1. The XTAL1 clock serves

as the basic timing reference for the baud rate genera-

tor, the C/T, and other internal circuits.

The

baud rate generator operates from the XTAL1 clock

input and can generate 28 commonly used data com-

munication baud rates (if a 3.6864MHz crystal or clock

is used) ranging from 50 to 230.4kbps by producing

internal clock outputs at 16 times the actual baud rate.

In addition, other baud rates can be derived by connect-

ing 16X or 1X clocks to multi-purpose input port pins IP3

- IP6 that have alternate functions as receiver or trans-

mitter clock inputs.

Clock selector logic consists of the clock selector

(MR0A, MR0B) and bit-7 of Auxilliary Control Register

(ACR). These allow various combinations of these baud

rates for receiver and transmitter of each channel. See

Baud Rate Table on page 18 for more details.

The

programmable 16-bit counter/timer (C/T) can pro-

duce a 16X clock for other baud rates by counting down

its programmed clock source. Users can program the

16 bit C/T within the XR88C92/192 to use one of several

clock sources as its input. The output of the C/T is

available to the internal clock selectors and can also be

programmed to appear at output OP3. In the timer mode,

the C/T acts as a programmable divider and can

generate a square-wave output at OP3. In the counter

mode, the C/T can be started and stopped under

program control. When stopped, the CPU can read its

contents. The counter counts down the number of

pulses stored in the concatenation of the C/T upper

rupt. This is a system-oriented feature that can be used

to record timeouts when implementing various applica-

tion protocols.

INTERRUPT CONTROL LOGIC

The following registers are associated with the interrupt

control logic:

· Interrupt Mask Register (IMR)

· Interrupt Status Register (ISR)

· Auxiliary Control Register (ACR)

A single active-low interrupt output (-INT) can notify the

CPU that any of eight internal events has occurred.

These eight events are described in the discussion of

the interrupt status register (ISR). User can program the

interrupt mask register (IMR) to allow only certain

conditions to cause -INT to be asserted while the CPU

can read the ISR to determine all currently active

interrupting conditions. In addition, users can program

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