PSD833F2 datasheet(66/110 Pages) STMICROELECTRONICS

66 / 110 page

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

66/110

PSD Chip Select Input (CSI, PD2)

PD2 of Port D can be configured in PSDsoft Ex-

press as PSD Chip Select Input (CSI). When Low,

the signal selects and enables the internal Flash

memory, EEPROM, SRAM, and I/O blocks for

READ or WRITE operations involving the PSD. A

High on PSD Chip Select Input (CSI, PD2) dis-

ables the Flash memory, EEPROM, and SRAM,

and reduces the PSD power consumption. How-

ever, the PLD and I/O signals remain operational

when PSD Chip Select Input (CSI, PD2) is High.

There may be a timing penalty when using PSD

Chip Select Input (CSI, PD2) depending on the

speed grade of the PSD that you are using. See

the timing parameter tSLQV in Table 61., page 94

or Table 62., page 95.

Input Clock

The PSD provides the option to turn off CLKIN

(PD1) to the PLD to save AC power consumption.

CLKIN (PD1) is an input to the PLD AND Array and

the Output Macrocells (OMC).

During Power-down mode, or, if CLKIN (PD1) is

not being used as part of the PLD logic equation,

the clock should be disabled to save AC power.

CLKIN (PD1) is disconnected from the PLD AND

Array or the Macrocells block by setting Bits 4 or 5

to a 1 in PMMR0.

Input Control Signals

The PSD provides the option to turn off the input

control signals (CNTL0, CNTL1, CNTL2, Address

Strobe (ALE/AS, PD0) and DBE) to the PLD to

save AC power consumption. These control sig-

nals are inputs to the PLD AND Array. During

Power-down mode, or, if any of them are not being

used as part of the PLD logic equation, these con-

trol signals should be disabled to save AC power.

They are disconnected from the PLD AND Array

by setting Bits 2, 3, 4, 5, and 6 to a 1 in PMMR2.

Table 32. APD Counter Operation

APD Enable Bit

ALE PD Polarity

ALE Level

APD Counter

Not Counting

Pulsing

Not Counting

Counting (Generates PDN after 15 Clocks)

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