74LVC38APW datasheet(8/14 Pages) PHILIPS

8 / 14 page

2004 Mar 22

Philips Semiconductors

Product speciﬁcation

Quad 2-input NAND gate (open drain)

74LVC38A

AC WAVEFORMS

handbook, full pagewidth

MNA700

tPLZ

(3)

nY output

nA, nB input

VCC

(1)

VOL

(2)

GND

tPZL

(1)

Fig.6 The input nA, nB to output nY propagation delays.

(1) VM = 1.5 V at VCC ≥ 2.7 V.

VM = 0.5VCC at VCC < 2.7 V.

(2) VOL and VOH are typical output voltage drop that occur with the output load.

(3) VX =VOL + 0.3 V at VCC ≥ 2.7 V.

VX =VOL + 0.15 V at VCC < 2.7 V.

Fig.7 Load circuitry for switching times.

Definitions for test circuits:

RL = Load resistor.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.

tr =tf ≤ 2.5 ns; when measuring fmax, there is no constraint on tr, tf with 50% duty factor.

Note

1. The circuit performs better when RL = 1000 Ω.

VCC

VEXT

1.2

× VCC

VCC

30 pF

500

Ω(1)

2.7

6 V

2.7 V

50 pF

500

Ω

3.3 to 3.6

6 V

2.7 V

50 pF

500

Ω

handbook, full pagewidth

VEXT

VCC

MNA616

D.U.T.

PULSE

GENERATOR

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