MB39C014 datasheet(12/32 Pages) CYPRESS

12 / 32 page

Document Number: 002-08361 Rev. *C

Page 12 of 32

MB39C014

(Ta

= + 25°C, VDD = 3.7 V, VOUT setting value = 2.5 V, MODE = 0 V)

*1 : The minimum value of VDD is the 2.5 V or VOUT setting value

+ 0.6 V, whichever is higher.

*2 : The

+ leak at the LX pin includes the current of the internal circuit.

*3 : Detected with respect to the output voltage setting value of VREFIN

*4 : Current consumption based on 100% ON-duty (High side FET in full ON state). The SW FET gate drive current is not included because the device is in full ON state

(no switching operation). Also the load current is not included.

Parameter

Symbol Pin No.

Condition

Value

Unit

Min

Typ

Max

POWER

GOOD block

POWERGOOD

threshold

voltage

VTHPG

VREFIN × 3

× 0.93

VREFIN × 3

× 0.97

VREFIN × 3

× 0.99

POWERGOOD

delay time

tDLYPG1

FSEL

= 0 V

—

250

—

μs

tDLYPG2

FSEL

= 3.7 V

—

170

—

μs

POWERGOOD

output voltage

VOL

POWERGOOD = 250

μA—

—

0.1

POWERGOOD

output current

IOH

POWERGOOD

= 5.5 V

—

1.0

μA

Control block

CTL threshold

voltage

VTHHCT

—

0.55

0.95

1.45

VTHLCT

—

0.40

0.80

1.30

CTL pin

input current

IICTL

CTL

= 3.7 V

—

1.0

μA

FSEL threshold

voltage

VTHHFS

—2.96

—

VTHLFS

——

—

0.74

Reference

voltage block

VREF voltage

VREF

= −2.7 μA,

OUT

= −100 mA

1.176

1.200

1.224

VREF load

stability

LOADREF

VREF

= −1.0 mA

—

General

Shut down

power supply

current

IVDD1

CTL

= 0 V,

All circuits in OFF state

——

1.0

μA

IVDD1H

CTL

= 0 V, VDD = 5.5 V

—

1.0

μA

Standby power

supply current

(DC/DC)

IVDD2

CTL

= 3.7 V, OUT = 0 A,

FSEL

= 0 V

—4.0

8.0

Power-on

invalid current

IVDD

CTL

= 3.7 V,

VOUT

= 90%*4

—

800

1500

μA

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