84330BV

www.icst.com/products/hiperclocks.html

REV. B JULY 26, 2004

12

Integrated

Circuit

Systems, Inc.

ICS84330

If the FREF_EXT input is driven by a 3.3V LVCMOS driver, the

jitter performance can be improved by reducing the amplitude

swing and slowing down the edge rate.

Figure 7A shows an

amplitude reduction approach for a long trace. The swing will

be approximately 0.85V for logic low and 2.5V for logic high

R2

100

VDD

R1

100

Ro ~ 7 Ohm

Driver_LVCMOS

Zo = 50 Ohm

Td

RS

43

VDD

VDD

GND

TEST_CLK

VDD

VDD

GND

TEST_CLK

R1

200

RS

100

Ro ~ 7 Ohm

Driver_LVCMOS

R2

200

VDD

VDD

VDD

R1

400

R2

400

Ro ~ 7 Ohm

Driver_LVCMOS

RS

200

VDD

GND

TEST_CLK

(instead of 0V to 3.3V).

Figure 7B shows amplitude reduction

approach for a short trace. The circuit shown in

Figure 7C

reduces amplitude swing and also slows down the edge rate

by increasing the resistor value.

FREF_EXT

FREF_EXT

FREF_EXT