| 전자부품 데이터시트 검색엔진 |
|
MB91F467BA 데이터시트(PDF) 92 Page - Cypress Semiconductor |
|
|
|||||||||||||||||||||||||||||
MB91F467BA 데이터시트(HTML) 92 Page - Cypress Semiconductor |
|
92 / 127 page ![]() MB91460B Series Document Number: 002-04608 Rev. *A Page 91 of 126 14. Recommended Settings 14.1 PLL and Clock Gear Settings Please note that for MB91F467BA/466BA and MB91F465BB/464BB the core base clock frequencies are valid in the 1.8V operation mode of the Main regulator and Flash. Table 7. Recommended PLL divider and clock gear settings PLL Input (CLK) [MHz] Frequency Parameter Clockgear Parameter PLL Output (X) [MHz] Core Base Clock [MHz] Remarks DIVM DIVN DIVG MULG MULG 4 2 25 16 24 200 100 Not on MB91F467BA/46 6BA 4 2 24 16 24 192 96 4 2 23 16 24 184 92 4 2 22 16 24 176 88 4 2 21 16 20 168 84 4 2 20 16 20 160 80 4 2 19 16 20 152 76 4 2 18 16 20 144 72 4 2 17 16 16 136 68 4 2 16 16 16 128 64 4 2 15 16 16 120 60 4 2 14 16 16 112 56 4 2 13 16 12 104 52 4 2 12 16 12 96 48 4 2 11 16 12 88 44 4 4 10 16 24 160 40 4 4 9 16 24 144 36 4 4 8 16 24 128 32 4 4 7 16 24 112 28 4 6 6 16 24 144 24 4 8 5 16 28 160 20 4 10 4 16 32 160 16 4 12 3 16 32 144 12 |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |