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MB91F469GA 데이터시트(PDF) 89 Page - Cypress Semiconductor |
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MB91F469GA 데이터시트(HTML) 89 Page - Cypress Semiconductor |
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89 / 147 page ![]() MB91460G Series Document Number: 002-04606 Rev. *A Page 88 of 146 14. Recommended Settings 14.1 PLL and Clock Gear Settings Please note that for MB91F469Gx core base clock frequencies above 88MHz can only be achieved with 1.9V core supply voltage [1]. Table 5. Recommended PLL divider and clockgear settings 1. In order to enter this mode please set REGSEL_FLASHSEL=1 and REGSEL_MAINSEL=1 (HWM Chapter 52.3.1) PLL Input (CLK) [MHz] Frequency Parameter Clockgear Parameter PLL Output (X) [MHz] Core Base Clock [MHz] 1.8V 1.9V DIVM DIVN DIVG MULG MULG 4 2 25 16 24 200 100 no yes 4 2 24 16 24 192 96 no yes 4 2 23 16 24 184 92 no yes 4 2 22 16 24 176 88 yes yes 4 2 21 16 20 168 84 yes yes 4 2 20 16 20 160 80 yes yes 4 2 19 16 20 152 76 yes yes 4 2 18 16 20 144 72 yes yes 4 2 17 16 16 136 68 yes yes 4 2 16 16 16 128 64 yes yes 4 2 15 16 16 120 60 yes yes 4 2 14 16 16 112 56 yes yes 4 2 13 16 12 104 52 yes yes 4 2 12 16 12 96 48 yes yes 4 2 11 16 12 88 44 yes yes 4 4 10 16 24 160 40 yes yes 4 4 9 16 24 144 36 yes yes 4 4 8 16 24 128 32 yes yes 4 4 7 16 24 112 28 yes yes 4 6 6 16 24 144 24 yes yes 4 8 5 16 28 160 20 yes yes 4 10 4 16 32 160 16 yes yes 4 12 3 16 32 144 12 yes yes |
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