MB91F522BJBPMC1 datasheet(2/280 Pages) CYPRESS

2 / 280 page

Document Number: 002-04662 Rev. *F

Page 2 of 280

MB91520 Series

 D/A converter (R-2R type)



8-bit resolution : 2 ch

 External interrupt input: 8 channels × 2 units total

16 channels



Level ("H" / "L"), or edge detection (rising or falling)

enabled

 Multi-function serial communication (built-in

transmission/reception FIFO memory) : Max.12 channels



5 V tolerant input: 4 channels ch.6, ch.8, ch.9, ch.11

CMOS hysteresis input

< UART (Asynchronous serial interface) >



Full-duplex double buffering system, 64-step

transmission FIFO memory, 64-step reception FIFO

memory



Parity or no parity is selectable.



Built-in dedicated baud rate generator



An external clock can be used as the transfer clock



Parity, frame, and overrun error detection functions

provided



DMA transfer support



Full-duplex double buffering system, 64-step

transmission FIFO memory, 64-step reception FIFO

memory



SPI supported; master and slave systems supported;

5 to 16, 20, 24, 32-bit data length can be set.



Built-in dedicated baud rate generator (Master

operation)



An external clock can be entered. (Slave operation)



Overrun error detection function is provided



DMA transfer support



Serial chip select SPI function



Full-duplex double buffering system, 64-step

transmission FIFO memory, 64-step reception FIFO

memory



LIN protocol revision 2.1 supported



Master and slave systems supported



Framing error and overrun error detection



LIN synch break generation and detection; LIN synch

delimiter generation



Built-in dedicated baud rate generator



An external clock can be adjusted by the reload

counter



DMA transfer support



Hard assist function

< I2C >



2 channels ch.3 , ch.4

Standard mode/fast mode

supported.



6 channels ch.5 to ch.8, ch.10, ch.11 Standard mode

supported.



Full-duplex double buffering system, 64-step

transmission FIFO memory, 64-step reception FIFO

memory



Standard mode (Max. 100 kbps) / fast mode (Max. 400

kbps) supported



DMA transfer supported (for transmission only)

 CAN Controller (CAN) : 3 channels



Transfer speed : Up to 1 Mbps



128-transmission/reception message buffering :

1 channel (ch.0),

64-transmission/reception message buffering :

2 channels (ch.1 and ch.2)

 PPG: 16-bit × Max. 48 channels



LED drive output 4 channels 11 ch to 14 ch



Reload timer : 16-bit × Max.8 channels



Free-run timer :

16-bit × 3 channels

32-bit × Max 3 channels

 Input capture :

16-bit × 4 channels (linked to the free-run timer)

32-bit × Max 6 channels (linked to the free-run timer)

 Output compare :

16-bit × 6 channels (linked to the free-run timer)

32-bit × Max 6 channels (linked to the free-run timer)

 Waveform generator : 6 channels

 Up/Down counter



8-/16-bit Up/Down counter × 2 channels

 Real-time clock (RTC) (for day, hours, minutes, seconds)



Main or sub oscillation frequency can be selected for

the operation clock

 Calibration: Real-time clock (RTC) of the subclock drive



The main clock to sub clock ratio can be corrected by

setting the real-time clock prescaler

 Clock Supervisor



Monitoring abnormality (by damaged quartz, etc.) of

suboscillation (32 kHz) (dual clock products)

of the outside and main oscillation (4 MHz)



When abnormality is detected, it switches to the CR

clock.



Initial value ON/OFF can be selected by the part

number.

 Base timer : Max.2 channels



16-bit timer



Any of four PWM/PPG/PWC/reload timer functions can

be selected and used



As for the PWC function and the reload timer function,

a pair of 16-bit timers can be used as one 32-bit timer

in the cascade mode

 CRC generation

 Watchdog timer



Hardware watchdog



Software watchdog (possible to set the valid range for

counter clearing)

 NMI (non-maskable interrupt)

 Interrupt controller

 Interrupt request batch read



The interrupt existence from two or more peripherals

can be read by a series of register.

 I/O relocation



Peripheral function pins can be reassigned.

 Low-power consumption mode



Sleep / Stop / Watch / Sub RUN mode



Stop (power shutdown) / Watch (power shutdown)

mode

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