S70FS01GS datasheet(80/141 Pages) CYPRESS

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S70FS01GS

Document Number: 002-03833 Rev. *C

Page 80 of 141

This command is also supported in QPI mode. In Quad AIl mode the instruction is shifted in on IO0-IO3, two clock cycles per byte.

Figure 9.7

Write Enable (WREN) Command Sequence QPI Mode

9.3.2

Write Disable (WRDI 04h):

The Write Disable (WRDI) command clears the Write Enable Latch (WEL) bit of the Status Register-1 (SR1V[1]) to a “0”.

The Write Enable Latch (WEL) bit may be cleared to a “0” by issuing the Write Disable (WRDI) command to disable Page Program

(PP), Sector Erase (SE), Bulk Erase (BE), Write Registers (WRR or WRAR), OTP Program (OTPP), and other commands, that

require WEL be set to “1” for execution. The WRDI command can be used by the user to protect memory areas against inadvertent

writes that can possibly corrupt the contents of the memory. The WRDI command is ignored during an embedded operation while

WIP bit =1.

CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI. Without CS# being

driven to the logic high state after the eighth bit of the instruction byte has been latched in on SI, the write disable operation will not

be executed.

Figure 9.8

Write Disable (WRDI) Command Sequence

This command is also supported in QPI mode. In Quad AIl mode the instruction is shifted in on IO0-IO3, two clock cycles per byte.

Figure 9.9

Write Disable (WRDI) Command Sequence QPI Mode

CS#

SCLK

IO0

IO1

IO2

IO3

Phase

Instruction

CS#

SCK

Phase

Instruction

CS#

SCLK

IO0

IO1

IO2

IO3

Phase

Instruction

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