TLF10176

June 1989

54LS114

Dual JK Negative Edge-Triggered

Flip-Flop with Common Clocks and Clears

General Description

The ’LS114 features individual J K and set inputs and com-

mon clock and common clear inputs When the clock goes

HIGH the inputs are enabled and data will be accepted The

logic level of the J and K inputs may be allowed to change

when the Clock Pulse is HIGH and the bistable will perform

according to the truth table as long as the minimum setup

times are observed Input data is transferred to the outputs

on the negative-going edge of the clock pulse

Connection Diagram

Dual-In-Line Package

TLF10176 – 1

Order Number 54LS114DMQB

54LS114FMQB or 54LS114LMQB

See NS Package Number E20A J14A or W14B

Logic Symbol

TLF10176 – 2

Pin Names

Description

J1 J2 K1 K2

Data Inputs

CP

Clock Pulse Input (Active Falling Edge)

CD

Direct Clear Input (Active LOW)

SD1 SD2

Direct Set Inputs (Active LOW)

Q1 Q2 Q1 Q2

Outputs

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A