EMIF03-SIM01

6/11

To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical

dynamic resistance value Rd. By taking into account these following hypothesis : R>>Rd, Rg>>Rd and

Rload>>Rd, it gives these formulas:

Vinput

RV

RV

R

gbr

d

g

g

=

⋅+⋅

Voutput

RV

R V

R

br

d

in

=

⋅+⋅

The results of the calculation done for an IEC 1000-4-2 Level 4 Contact Discharge surge (Vg=8kV,

Rg=330

Ω ) and Vbr=7V (typ.) give:

Vinput = 43.36V

Voutput = 7.65V (R = 100

Ω)

8.38V (R = 47

Ω)

This confirms the very low remaining voltage across the device to be protected. It is also important to note

that in this approximation the parasitic inductance effect was not taken into account. This could be few

tenths of volts during few ns at the Vin side. This parasitic effect is not present at the Vout side due the low

current involved after the series resistance R.

The early ageing and destruction of IC’s is often due to latch-up phenomena which mainly induced by

dV/dt. Thanks to its RC structure, the EMIF03-SIM01 provides a high immunity to latch-up by integration of

fast edges. (Please refer to the response of the EMIF03-SIM01 to a 30 ns edge on Fig. A9)

The measurements done here after show very clearly (Fig. A5a & A5b) the high efficiency of the ESD

protection :

- almost no influence of the parasitic inductances on Vout stage

- Vout clamping voltage very close to Vbr for positive surge and close to ground for negative one

LATCH-UP PHENOMENA

TEST BOARD

EMI03

SIM01

V(in)

V(out)

Fig. A4: Measurements conditions