RFHCS362F datasheet(27/60 Pages) MICROCHIP

27 / 60 page

Preliminary

DS41189A-page 27

rfHCS362G/362F

5.0

PROGRAMMING THE

rfHCS362G/362F

When using the rfHCS362G/362F in a system, the user

will have to program some parameters into the device,

including the serial number and the secret key before it

can be used. The programming cycle allows the user to

input all 288 bits in a serial data stream, which are then

stored internally in EEPROM. Programming will be

initiated by forcing the DATA line HIGH, after the S2 line

has been held HIGH for the appropriate length of time

(Table 10-3 and Figure 5-1). After the Program mode is

entered, a delay must be provided to the device for the

automatic bulk write cycle to complete. This will write all

locations in the EEPROM to an all zeros pattern includ-

ing the OSC calibration bits.

The device can then be programmed by clocking in 16

bits at a time, using S2 as the clock line and DATA as

the data in-line. After each 16-bit word is loaded, a pro-

gramming delay is required for the internal program

cycle to complete. This delay can take up to Twc. At the

end of the programming cycle, the device can be veri-

fied (Figure 5-2) by reading back the EEPROM. Read-

ing is done by clocking the S2 line and reading the data

bits on DATA. For security reasons, it is not possible to

execute a Verify function without first programming the

EEPROM. A Verify operation can only be done

once, immediately following the Program cycle.

FIGURE 5-1:

PROGRAMMING WAVEFORMS

FIGURE 5-2:

VERIFY WAVEFORMS

Note:

To ensure that the device does not

accidentally enter Programming mode,

DATA should never be pulled high by

the circuit connected to it. Special care

should be taken when driving circuits

other than the RFENIN.

DATA

Enter Program

Mode

(Data)

(Clock)

Note 1: Unused button inputs to be held to ground during the entire programming sequence.

Bit 0

Bit 1

Bit 2

Bit 3

Bit 14

Bit 15

Bit 16

Bit 17

TPH1

TPBW

TPS

Repeat for each word (18 times)

TPH2

TCLKH

TCLKL

TWC

TDS

S2 (S3)

Data for Word 0 (KEY_0)

Data for Word 1

TDH

2: The VDD pin must be taken to ground after a Program/Verify cycle.

DATA

(Clock)

(Data)

Note: If a Verify operation is to be done, then it must immediately follow the Program cycle.

End of Programming Cycle

Beginning of Verify Cycle

Bit 1 Bit 2

Bit 3

Bit 15

Bit 14

Bit 16 Bit 17

Bit286 Bit287

TWC

Data from Word 0

TDV

S2 (S3)

Bit 0

Bit287

Bit286

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