RFHCS362G datasheet(19/60 Pages) MICROCHIP

19 / 60 page

Preliminary

DS41189A-page 19

rfHCS362G/362F

FIGURE 3-10: SEED CODE WORD FORMAT

3.4

Seed Code Word Data Format

A seed transmission transmits a unencrypted code

word that consists of 60 bits of fixed data that is stored

in the EEPROM. This can be used for secure learning

of encoders or whenever a fixed code transmission is

required. The seed code word further contains the

function code and the status information (VLOW, CRC

and QUEUE) as configured for normal code hopping

code words. The seed code word format is shown in

Figure 3-10. The function code for seed code words is

always ‘1111b’.

Seed code words can be configured as follows:

• Enabled permanently.

• Disabled permanently.

• Enabled until the synchronization counter is

greater than 7Fh, this configuration is often

referred to as Limited Seed.

• The time before the seed code word is transmitted

can be set to 1.6 s or 3.2 s, this configuration is

often referred to as Delayed Seed. When this

option is selected, the rfHCS362 will transmit a

code hopping code word for 1.6 s or 3.2 s, before

the seed code word is transmitted.

3.4.1

SEED OPTIONS

The button combination (S[3210]) for transmitting a

Seed code word can be selected with the Seed and

SeedC (SEED[0..1] and SEEDC) configuration

options as shown in Table 3-1 and Table 3-2:

TABLE 3-1:

SEED OPTIONS (SEEDC = 0)

TABLE 3-2:

SEED OPTIONS (SEEDC = 1)

Example A): Selecting SEEDC = 1 and SEED = 11:

makes SEED transmission available every time the

combination of buttons S3 and S0 is pressed simulta-

neously, but Delayed Seed mode is not available.

Example B): Selecting SEEDC = 0 and SEED = 01:

makes SEED transmission available only for a limited

time (only up to 128 times). The combination of buttons

S2 and S0 produces an immediate transmission of the

SEED code. Pressing and holding for more than 1.6

seconds the S0 button alone produces the SEED code

word transmission (Delayed Seed).

Transmission Direction LSB First

Fixed Portion

QUE

(2 bits)

CRC

(2 bits)

VLOW

(1-bit)

SEED

With QUEN = 1

BUT

(4 bits)

(9 bits)

SEED Code

(60 bits)

Q1 Q0 C1 C0

Seed

1.6 s Delayed Seed

SEED

S[3210]

0101*

0001*

0101

0001

0101

Note:

*Limited Seed

Seed

3.2 s Delayed Seed

SEED

S[3210]

1001*

0011*

1001

0011

1001

Note:

*Limited Seed

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