MPC93R51

TIMING SOLUTIONS

9

MOTOROLA

Figure 11. Propagation delay (tPD, static phase

offset) test reference

Figure 12. Propagation delay (tPD) test reference

Figure 13. Output Duty Cycle (DC)

Figure 14. Output–to–output Skew tSK(O)

The pin–to–pin skew is defined as the worst case difference

in propagation delay between any similar delay path within a

single device

The time from the PLL controlled edge to the non controlled

edge, divided by the time between PLL controlled edges,

expressed as a percentage

VCC

VCCB2

GND

VCC

VCCB2

GND

tSK(O)

VCC

VCCB2

GND

tP

T0

DC = tP/T0 x 100%

VCC

VCCB2

GND

VCC

VCCB2

GND

t(

∅)

TCLK

Ext_FB

VCC

VCCB2

GND

t(

∅)

PCLK

Ext_FB

PCLK

VCMR

VCMR

Figure 15. Cycle–to–cycle Jitter

Figure 16. Period Jitter

The variation in cycle time of a signal between adjacent cycles, over a

random sample of adjacent cycle pairs

The deviation in cycle time of a signal with respect to the ideal period over

a random sample of cycles

TN

TJIT(CC) = |TN–TN+1|

TN+1

TJIT(P) = |TN–1/f0|

T0

tF

tR

VCC=3.3V

2.4

0.55

Figure 17. I/O Jitter

Figure 18. Transition Time Test Reference

TJIT(

∅) = |T0–T1mean|

TCLK

Ext_FB

The deviation in t0 for a controlled edge with respect to a t0 mean in a

random sample of cycles

(PCLK)

Freescale Semiconductor, Inc.

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