Document Number: 002-01122 Rev.*L

Page 45 of 59

S29AS016J

18.2

Hardware Reset (RESET#)

Note

Not 100% tested.

Figure 18.2 RESET# Timings

Note

1. CE# should only go low after RESET# has gone high. Keeping CE# low from power up through the first read could cause the first read to retrieve erroneous data.

Parameter

Description

All Speed Options

JEDEC

Std

Test Setup

Unit

RESET# Pin Low (During Embedded Algorithms) to

Read or Write (See Note)

Max

35

µs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note)

Max

500

ns

RESET# Pulse Width

Min

500

RESET# High Time Before Read (See Note)

50

RESET# Low to Standby Mode

20

µs

RY/BY# Recovery Time

0

ns

RESET#

RY/BY#

RY/BY#

Reset Timings NOT during Embedded Algorithms (Note 1)

CE#, OE#

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#