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VBUS54GD-FBL 데이터시트(PDF) 2 Page - Vishay Siliconix |
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VBUS54GD-FBL 데이터시트(HTML) 2 Page - Vishay Siliconix |
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2 / 8 page ![]() VBUS54GD-FBL www.vishay.com Vishay Semiconductors Rev. 1.2, 03-May-17 2 Document Number: 85916 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 APPLICATION NOTE The VBUS54GD-FBL is a four-line ESD protection device with the characteristic of a Z-diode with a high ESD immunity and a very low capacitance which makes it usable for high frequency applications like USB2.0, USB3.0 or HDMI. With the VBUS54GD-FBL four high speed data lines can be protected against transient voltage signals like ESD (electro static discharge). Connected to the data line (pin 1, 2 and pin 4, 5) and to ground (pin 3 and 8) negative transients will be clamped close below the ground level while positive transients will be clamped close above the 5.5 V working range. The clamping behavior of the VBUS54GD-FBL is bidirectional but asymmetrical (BiAs) and so it offers the best protection for applications running up to 5.5 V. Pin configuration: • Pin 3 and 8 are internally shorted and have to be connected to ground • Pin 1, 2 and 4, 5 are the inputs for the data lines D1+ and D1- and D2+ and D2- • Pin 6, 7 and 9, 10 are not connected internally FLOW THROUGH DESIGN Modern digital transmission lines can be clocked up to 480 Mbit/s (USB2.0) or 1.65 Gbit/s (HDMI). At such high data rates the transmission lines like cables or the line traces on the PCBs have to be very homogeneous regarding their surge impedance. This requires well defined trace dimensions as trace width and distance which have to be calculated depending on the requested surge impedance (e.g. 50 ) and the PCB material and layer dimensions. Any device connected to the data lines - like ESD protection devices - have to be connected with minimal changes in these trace dimensions and distances. With the package in the so called “Flow Through Design” this is possible. The lines are running straight along the PCB while the VBUS54GD-FBL is placed on top without any via or loops. ELECTRICAL CHARACTERISTICS VBUS54GD-FBL (PIN 1, 2, 4 OR 5 TO PIN 3) (Tamb = 25 °C, unless otherwise specified) PARAMETER TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. MAX. UNIT Protection paths Number of lines which can be protected Nchannel - - 4 lines Reverse stand-off voltage Max. reverse working voltage VRWM -- 5.5 V Reverse voltage at IR = 0.1 μA VR 5.5 - - V Reverse current at VRWM = 5.5 V IR - 0.02 0.1 μA Reverse breakdown voltage at IR = 1 mA VBR 6.9 7.5 8.7 V Reverse clamping voltage at IPP = 1 A VC -9.1 11 V at IPP = IPPM = 3 A VC -12 15 V Forward clamping voltage at IPP = 1 A VF -2.1 2.4 V at IPP = 3 A VF -3.5 4.5 V Clamping voltage Transmission line pulse (TLP), tp = 100 ns ITLP = 8 A VC-TLP -15- V Transmission line pulse (TLP), tp = 100 ns ITLP = 16 A VC-TLP -21- V Dynamic resistance Transmission line pulse (TLP), tp = 100 ns RDYN -0.76 - Capacitance at VR = 0 V; f = 1 MHz CD -0.6 0.75 pF at VR = 3.3 V; f = 1 MHz - 0.65 0.75 pF Capacitance between I/O lines at VR = 3.3 V; f = 1 MHz CDD -0.3 0.4 pF nc. GND GND D2+ 123 4 5 98 76 nc. nc. nc. D2- D1+ D1- 22552 10 123 4 5 10 9 8 7 6 USB / HDMI Interface D2+ D2- D1+ D1- GND D2+ D2- D1+ D1- I/O Port Connector ------ 22553 |
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