ADC08038CIWM datasheet(12/24 Pages) NSC

12 / 24 page

Functional Description (Continued)

TABLE 4. MUX Addressing: ADC08034

Single-Ended MUX Mode

MUX Address

Channel #

START

SGL/

ODD/

SELECT

0123

DIF

SIGN

COM is internally tied to AGND

MUX Addressing:

ADC08032

Single-Ended MUX Mode

MUX Address

Channel #

START

SGL/

ODD/

DIF

SIGN

COM is internally tied to AGND

Differential MUX Mode

MUX Address

Channel #

START

SGL/

ODD/

SELECT

0123

DIF

SIGN

−

Differential MUX Mode

MUX Address

Channel #

START

SGL/

ODD/

DIF

SIGN

−

Since the input configuration is under software control, it can

be modified as required before each conversion. A channel

can be treated as a single-ended, ground referenced input

for one conversion; then it can be reconfigured as part of a

differential channel for another conversion.

Figure 1 illus-

trates the input flexibility which can be achieved.

The analog input voltages for each channel can range from

50mV below ground to 50mV above V

CC (typically 5V) with-

out degrading conversion accuracy.

2.0 THE DIGITAL INTERFACE

A most important characteristic of these converters is their

serial data link with the controlling processor. Using a serial

communication format offers two very significant system im-

provements; it allows many functions to be included in a

small package and it can eliminate the transmission of low

level analog signals by locating the converter right at the

analog sensor; transmitting highly noise immune digital data

back to the host processor.

To understand the operation of these converters it is best to

refer to the Timing Diagrams and Functional Block Diagram

and to follow a complete conversion sequence. For clarity a

separate timing diagram is shown for each device.

A conversion is initiated by pulling the CS (chip select)

line low. This line must be held low for the entire conver-

sion. The converter is now waiting for a start bit and its

MUX assignment word.

On each rising edge of the clock the status of the data in

(DI) line is clocked into the MUX address shift register.

The start bit is the first logic “1” that appears on this line

(all leading zeros are ignored). Following the start bit the

converter expects the next 2 to 4 bits to be the MUX as-

signment word.

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