CS5530A datasheet(29/259 Pages) NSC

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Signal Definitions (Continued)

SMEMW#/

FP_HSYNC_OUT

Limited ISA Mode: Flat Panel Horizontal Sync Output

Refer to Section 2.2.11 "Display Interface" on page 35 for this signal’s defini-

tion.

Note that if Limited ISA Mode of operation is selected, SMEMW# is available

on pin AF3 (multiplexed with RTCCS#).

ISA Master Mode: System Memory Write

SMEMW# is asserted for any memory write accesses below 1 MB (i.e.,

A23:A20 set to 0). This enables 8-bit memory slaves to decode the memory

address on SA[19:0].

SMEMR#/

FP_VSYNC_OUT

Limited ISA Mode: Flat Panel Vertical Sync Output

Refer to Section 2.2.11 "Display Interface" on page 35 for this signal’s defini-

tion.

Note that if Limited ISA Mode of operation is selected, SMEMR# is available

on pin AD4 (multiplexed with RTCALE).

ISA Master Mode: System Memory Read

SMEMR# is asserted for memory read accesses below 1 MB (i.e., A23:A20

set to 0). This enables 8-bit memory slaves to decode the memory address

on SA[19:0].

SMEMW#/

RTCCS#

AF3

System Memory Write / Real-Time Clock Chip Select

If Limited ISA Mode of operation has been selected, then SMEMW# can be

output on this pin. SMEMW# is asserted for any memory write accesses

below 1 MB (i.e., A23:A20 set to 0). This enables 8-bit memory slaves to

decode the memory address on SA[19:0].

RTCCS# is a chip select to an external real-time clock chip. This signal is

activated on reads or writes to I/O Port 071h.

Function selection is made through F0 Index 53h[2]: 0 = SMEMW#,

1= RTCCS#.

SMEMR#/

RTCALE

AD4

System Memory Read / Real-Time Clock Address Latch Enable

If Limited ISA Mode of operation has been selected, then SMEMR# can be

output on this pin. SMEMR# is asserted for memory read accesses below 1

MB (i.e., A23:A20 set to 0). This enables 8-bit memory slaves to decode the

memory address on SA[19:0].

RTCALE is a signal telling an external real-time clock chip to latch the

address, which is on the SD bus.

Function selection is made through F0 Index 53h[2]: 0 = SMEMR#,

1= RTCALE.

SBHE#

AE17

I/O

(PU)

System Bus High Enable

The CS5530A or ISA master asserts SBHE# to indicate that SD[15:8] will be

used to transfer a byte at an odd address.

SBHE# is an output during non-ISA master DMA operations. It is driven as

the inversion of AD0 during 8-bit DMA cycles. It is forced low for all 16-bit

DMA cycles.

SBHE# is an input during ISA master operations.

This pin is internally connected to a 20-kohm pull-up resistor.

BALE

AF9

Buffered Address Latch Enable

BALE indicates when SA[23:0] and SBHE# are valid and may be latched.

For DMA transfers, BALE remains asserted until the transfer is complete.

2.2.5

ISA Bus Interface (Continued)

Signal Name

No.

Type

Description

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