OV7410 datasheet(12/18 Pages) ETC

12 / 18 page

OV7910P/OV7410P/OV7411P

Version 1.4

December 7, 1999

SINGLE IC CMOS COLOR & B/W PAL ANALOG CAMERAS

OMNIVISION TECHNOLOGIES, Inc.

Preliminary

below).

Figure 4. Bit Transfer on the I2C Bus

SDA

SCL

DATA

STABLE

DATA

CHANGE

ALLOWED

2.1

I2C Bus Protocol Format

In I2C operation, the master must perform the following

operations:

n Generate the start/stop condition

n Provide the serial clock on SCL

n Place the 7-bit slave address, the RW bit,

and the 8-bit subaddress on SDA

The receiver must pull down SDA during the acknowl-

edge bit time. During the write cycle, the OV7910P/

OV7410P/OV7411P device returns the acknowledg-

ment and, during read cycle, the master returns the

acknowledgment except when the read data is the last

byte. If the read data is the last byte, the master does

not perform an acknowledge, indicating to the slave

that the read cycle can be terminated. Note that the

restart feature is not supported here.

Within each byte, MSB is always transferred first.

Read/write control bit is the LSB of the first byte. Stan-

dard I2C communications require only two pins: SCL

and SDA. SDA is configured as open drain for bidirec-

tional purpose. A HIGH to LOW transition on the SDA

while SCL is HIGH indicates a START condition. A

LOW to HIGH transition on the SDA while SCL is HIGH

indicates a STOP condition. Only a master can gener-

ate START/STOP conditions.

Except for these two special conditions, the protocol

that SDA remain stable during the HIGH period of the

clock, SCL. Each bit is allowed to change state only

when SCL is LOW (See Figure 4. Bit Transfer on the

I2C Bus and Figure 5. Data Transfer on the I2C Bus

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