DLR2416, DLO2416, DLG2416

2006-01-23

8

IDCD5036

1

0

200 µs

Blanking Pulse Width

4 µs min., 196 µs max.

5 kHz Blanking Frequency

~

~

~

~

Loading Data

Setting the chip enable (CE1, CE2) to their true state will

enable data loading. The desired data code (D0-D6) and

digit address (A0, A1) must be held stable during the

write cycle for storing new data.

Data entry may be asynchronous and random. Digit 0 is

defined as right hand digit with A1=A2=0.

To clear the entire internal four-digit memory hold the

clear (CLR) low for 1.0 µs. All illuminated dots will be

turned off within one complete display multiplex cycle,

1.0 ms minimum. The clear function will clear both the

ASCII RAM and the cursor RAM.

Loading Cursor

Setting the chip enables (CE1, CE2) and cursor select

(CU) to their true state will enable cursor loading. A write

(WR) pulse will now store or remove a cursor into the

digit location addressed by A0, A1, as defined in data

entry. A cursor will be stored if D0=1 and will removed if

D0=0. The cursor (CU) pulse width should not be less

than the write (WR) pulse or erroneous data may appear

in the display.

If the cursor is not required, the cursor enable signal

(CUE) may be tied low to disable the cursor function. For

a flashing cursor, simply pulse CUE. If the cursor has

been loaded to any or all positions in the display, then

CUE will control whether the cursor(s) or the characters

will appear. CUE does not affect the contents of cursor

memory.

Display Blanking

Blanking the display may be accomplished by loading a

blank or space into each digit of the display or by using

the (BL) display blank input.

Setting the (BL) input low does not affect the contents of

either data or cursor memory.

A flashing circuit can easily be constructed using a 555

as table multivibrator. Figure 4 illustrates a circuit in

which varying R2 (100K~10K) will have a flash rate of

1.0 Hz~10 Hz.

The display can be dimmed by pulse width modulating

the (BL) at a frequency sufficiently fast to not interfere

with the internal clock. The dimming signal frequency

should be 2.5 kHz or higher. Dimming the display also

reduces power consumption.

An example of a simple dimming circuit using a 556 is

illustrated in Figure 5. Adjusting potentiometer R3 will

dim the display by changing the blanking pulse duty

cycle.

Design Considerations

For details on design and applications of the DLX2416

using standard bus configurations in multiple display sys-

tems, or parallel I/O devices, such as the 8255 with an

8080 or memory mapped addressing on processors such

as the 8080, Z80, 6502, or 6800, refer to Appnote 14 at

www.osram-os.com.

DLX2416—Flashing Circuit Using a 555 and

Flashing (Blanking) Timing

DLX2416—Dimming Circuit Using a 556 and

Dimming (Blanking) Timing

IDCD5033

Timer

555

1

2

3

4

7

8

6

5

1

R

4.7 k

Ω

100 k

Ω

10 µF

0.01 µF

CC

V

= 5 V

To BL

Pin on

Display

IDCD5035

1

0

500 ms

Blanking Pulse Width

50% Duty Factor

2 Hz Blanking Frequency

~

~

~

~

~

~

IDCD5034

Dual Timer

556

1

2

3

4

13

14

12

11

500 k

Ω

1000 pF

CC

V

= 5 V

6

7

5

9

8

10

C

0.01 µF

4

0.01 µF

2

47 k

R

Ω

200

Ω

4700 pF

Control

Dimming (Blanking)

To BL Pin

on Display