MLX90313

Programmable IR Sensor Interface

MLX90313 Programmable IR sensor Interface

Page 21

Rev 1.0 21-July-2001

3901090313

Eeprom Description

MLX90313 contains 128 x 16 EEPROM memory. The memory can be accessed through the serial

interface. The 11 most significant bits are data bits and the 5 less significant bits are control bits used for

the Error Check and Correction system (ECC). After POR the ASIC reads the full eeprom contents,

checks it and corrects the single errors (1 wrong bit per address). If higher order error is discovered then

the bit ‘fatal error’ will be set (see Confreg1 description in previous section).

The memory has two levels of protection. After POR the write access to the eeprom will be disabled. The

external unit can remove this level of protection writing proper data in WP register. In this case all

addresses in range 08-77h will be available for write access. The first and last 8 addresses will still be

disabled. The write access to these cells is available only if the write protection is removed and the chip is

in test mode.

Eeprom map overview

Address list eeprom

Address

Write access

Register name

Function

Dec

Hex

IRGAIN1

IR-chain settings

0

00h

test mode**

IRGAIN2

IR-chain settings

1

01h

test mode

TEMPGAIN

Temp-chain settings

2

02h

test mode

CONFREG1

Configuration

3

03h

test mode

CONFREG2

Configuration

4

04h

test mode

OSCCTRL

Oscillator control

5

05h

test mode

BGCTRL

Bandgap control

6

06h

test mode

LPF

Low Pass Filter

7

07h

test mode

CALIBRATION

Look up table

linearisation.

8-111

08h-6Fh

WP*

IOS-TEMP

Initial offset Temp-chain

112

70h

WP

IOS-IR

Initial offset IR-chain

113

71h

WP

RESERVED

114

72h

WP

THCOMP1

Threshold for comparator

Comp1

115

73h

WP

HSCOMP1

Hysteresis for comparator

Comp1

116

74h

WP

THREL1

Threshold for comparator

of Rel1

117

75h

WP

HSREL1

Hysteresis for comparator

of Rel1

118

76h

WP

RESERVED

119

77h

CHIP-ID

Data

120-127

78h-7Fh

test mode

*WP: Write access to EEprom is controlled by the content of the internal register WP

**Test mode: Write access controlled by the internal register WP and only available in test mode

The last 8 addresses 0x78 to 0x7F are free to use for the user. They can hold some calibration data or

identification number. All data programmed into the eeprom must pass the error checking. Therefore, one

must add 5 hamming bits to the eeprom data, in the 5 least significant bits.