전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

MP4473GL 데이터시트(PDF) 19 Page - Monolithic Power Systems

부품명 MP4473GL
상세설명  High-Efficiency, Fast-Transient, 3.5A, 36V Synchronous, Step-Down Converter
PDF  21 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  MPS [Monolithic Power Systems]
홈페이지  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP4473GL 데이터시트(HTML) 19 Page - Monolithic Power Systems

Back Button MP4473GL Datasheet HTML 13Page - Monolithic Power Systems MP4473GL Datasheet HTML 14Page - Monolithic Power Systems MP4473GL Datasheet HTML 15Page - Monolithic Power Systems MP4473GL Datasheet HTML 16Page - Monolithic Power Systems MP4473GL Datasheet HTML 17Page - Monolithic Power Systems MP4473GL Datasheet HTML 18Page - Monolithic Power Systems MP4473GL Datasheet HTML 19Page - Monolithic Power Systems MP4473GL Datasheet HTML 20Page - Monolithic Power Systems MP4473GL Datasheet HTML 21Page - Monolithic Power Systems  
Zoom Inzoom in Zoom Outzoom out
 19 / 21 page
background image
MP4473–HIGH-EFFICIENCY, FAST-TRANSIENT, SYNCHRONOUS, STEP-DOWN CONVERTER
MP4473 Rev. 1.0
www.MonolithicPower.com
19
12/15/2014
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
LAYOUT RECOMMENDATION
1. Place high-current paths (GND, IN, and SW)
very close to the device with short, direct, and
wide traces.
2. Place input capacitors on both VIN sides
(PIN8 and PIN19) and as close to the IN and
GND pins as possible.
3. Place the decoupling capacitor as close to
the Vcc and GND pins as possible.
4. Keep the switching node SW short and far
away from the feedback network.
5. Place the external feedback resistors next to
the FB pin. Do not place vias on the FB trace.
6. Keep the BST voltage path (BST, C3, and
SW) as short as possible.
7. Connect the bottom IN and SW pads to a
large copper area to achieve optimal thermal
performance.
8. A four-layer layout is strongly recommended
to achieve optimal thermal performance.
C2A
C2B
Top Layer
Inner1 Layer
Inner2 Layer
Bottom Layer
Figure 9: PCB Layout



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com