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SAFC161RI 데이터시트(PDF) 52 Page - Siemens Semiconductor Group

부품명 SAFC161RI
상세설명  16-Bit CMOS Single-Chip Microcontroller
PDF  60 Pages
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제조업체  SIEMENS [Siemens Semiconductor Group]
홈페이지  http://www.siemens.com/
Logo SIEMENS - Siemens Semiconductor Group

SAFC161RI 데이터시트(HTML) 52 Page - Siemens Semiconductor Group

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Semiconductor Group
52
1998-05-01
C161RI
1) RW-delay and t
A refer to the next following bus cycle.
2) It is guaranteed by design that read data are latched before the address changes.
Address hold after WR 2)
t
28
CC
0 +
t
F
–0 +
t
F
–ns
ALE falling edge to CS
t
38
CC
– 4 -
t
A
10 -
t
A
– 4 -
t
A
10 -
t
A
ns
CS low to Valid Data In
t
39
SR
–
74
+
t
C + 2tA
–
3TCL - 20
+
t
C + 2tA
ns
CS hold after RD, WR
t
41
CC
17 +
t
F
–TCL - 14
+
t
F
–ns
ALE falling edge to RdCS,
WrCS (with RW-delay)
t
42
CC
27 +
t
A
–TCL - 4
+
t
A
–ns
ALE falling edge to RdCS,
WrCS (no RW-delay)
t
43
CC
– 4 +
t
A
–– 4
+
t
A
–ns
RdCS to Valid Data In
(with RW-delay)
t
46
SR
–
39 +
t
C
–
2TCL - 24
+
t
C
ns
RdCS to Valid Data In
(no RW-delay)
t
47
SR
–
70 +
t
C
–
3TCL - 24
+
t
C
ns
RdCS, WrCS Low Time
(with RW-delay)
t
48
CC
53 +
t
C
–
2TCL - 10
+
t
C
–ns
RdCS, WrCS Low Time
(no RW-delay)
t
49
CC
84 +
t
C
–
3TCL - 10
+
t
C
–ns
Data valid to WrCS
t
50
CC
49 +
t
C
–
2TCL - 14
+
t
C
–ns
Data hold after RdCS
t
51
SR
0–0
–
ns
Data float after RdCS
(with RW-delay)
t
53
SR
–
43 +
t
F
–
2TCL - 20
+
t
F
ns
Data float after RdCS
(no RW-delay)
t
68
SR
–
11 +
t
F
–TCL - 20
+
t
F
ns
Address hold after
RdCS, WrCS
t
55
CC
– 10 +
t
F
–– 10
+
t
F
–ns
Data hold after WrCS
t
57
CC
17 +
t
F
–TCL - 14
+
t
F
–ns
Parameter
Symbol
Max. CPU Clock
= 16 MHz
Variable CPU Clock
1/2TCL = 1 to 16 MHz
Unit
min.
max.
min.
max.



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