The Smart Timing Choice



The Smart Timing Choice



SiT2018B

High Temp, Single-Chip, One-Output Clock Generator

Rev. 1.0

Page 4 of 12

www.sitime.com

Note:

7. SiT2018 has “no runt” pulses and “no glitch” output during startup or resume.

Figure 2. Test Circuit

Note:

6. Duty Cycle is computed as Duty Cycle = TH/Period.

Figure 3. Output Waveform

Timing Diagrams

Figure 4. Startup Timing (OE/ST Mode)

Figure 5. Standby Resume Timing (ST Mode Only)

u

Figure 6. OE Enable Timing (OE Mode Only)

Figure 7. OE Disable Timing (OE Mode Only)

5

1

4

3

0.1µF

Power

Supply

OE/ST Function

Test

Point

15 pF

(including probe

and fixture

capacitance)

Vdd

2

Vout

Vdd

1k

80% Vdd

High Pulse

(TH)

50%

20% Vdd

Period

Tf

Tr

Low Pulse

(TL)

90% Vdd

Vdd

Pin 4 Voltage

CLK Output

T_start

T_start: Time to start from power-off

No Glitch

during start up

[7]

HZ

50% Vdd

Vdd

ST Voltage

CLK Output

T_resume

T_resume: Time to resume from ST

HZ

50% Vdd

Vdd

OE Voltage

CLK Output

T_oe

T_oe: Time to re-enable the clock output

HZ

50% Vdd

Vdd

OE Voltage

CLK Output

T_oe: Time to put the output in High Z mode

HZ

T_oe