| 전자부품 데이터시트 검색엔진 |
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LM9801 데이터시트(PDF) 17 Page - National Semiconductor (TI) |
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LM9801 데이터시트(HTML) 17 Page - National Semiconductor (TI) |
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17 / 34 page ![]() TABLE II Configuration Register Parameters (Continued) Parameter Control Bits Result w 1 Enable w 1EN 0 w 1 Output Off 1 w 1 Output On w 2 Enable w 2EN 0 w 2 Output Off 1 w 2 Output On RS Enable RSEN 0 RS Output Off 1 RS Output On TR Enable TREN 0 TR Output Off 1 TR Output On (tTRWIDTH) TR Pulse Width TRW1 TRW0 0 0 20 tMCLK (10 ms) 0 1 30 tMCLK (15 ms) 1 0 40 tMCLK (20 ms) 1 1 50 tMCLK (25 ms) TR-w1 TRGRD Guardband 0 1tMCLK (50 ns) (tGUARD) 1 2tMCLK (100 ns) TR Polarity TRPOL 0 TR 1 TR Signal Polarity SIGPOL 0 Positive (CIS) 1 Negative (CCD) register than number in this should be one less dummy pixels in CCD Actual number of Register Value is 2 Note Minimum Dummy Pixels BLS6 BLS5 BLS4 BLS3 BLS2 BLS1 BLS0 Dummy Pixels 0000000 Not Valid 0000001 Not Valid 0000010 1 0000011 2 1111101 124 1111110 125 1111111 126 Register Value is 1 Note Minimum Optical Black Pixels BLL7 BLL6 BLL5 BLL4 BLL3 BLL2 BLL1 BLL0 Optical Black Pixels 00000000 Not Valid 00000001 1 00000010 2 00000011 3 11111101 253 11111110 254 11111111 255 Note tMCLK e 1fMCLK e 1 MCLK period Examples given in parenthesis are for fMCLK e 20 MHz (tMCLK e 50 ns) http www nationalcom 17 |
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