5

HT574

Symbol

Parameter

Conditions (1)

Typical

Min

Max

Units

tDSC

STS Delay from CE

200

ns

tHEC

CE Pulse Width

50

ns

tSSC

NCS to CE Setup

50

ns

tHCS

NCS Low during CE High

50

ns

tSRC

R_NC to CE Setup

50

ns

tHRC

R_NC Low during CE High

50

ns

tSAC

Ao to CE Setup

0

ns

tHAC

Ao Valid during CE High

50

ns

tC

Conversion Time

12-Bit Cycle

8-Bit Cycle

Including Acquisition

Tmin to Tmax

Tmin to Tmax

10

7.2

µs

µs

CONVERT MODE TIMING CHARACTERISTICS

CONVERT MODE TIMING DIAGRAM

READ MODE TIMING DIAGRAM

(1) Time is measured from 50% level of digital transitions. Tested with a 100pF and 3k

Ω load for high impedance to drive and

tested with 10pF and 3k

Ω load for drive to high impedance.

CE

Ao

STS

DB11-DB0

NCS

R_NC

tHEC

tC

tDSC

tHAC

tSAC

tHRC

tHSC

tSSC

tSRC

High Impedance

CE

Ao

STS

DB11-DB0

tSSR

tSRR

tSAR

High

Impedance

tHS

tHD

tHAR

tHRR

tHSR

NCS

R_NC

Data Valid

tDD

tHL

Temperature ranges = -55 to +225

°C, VDD = 10.0V ±10%

Typical @ +25

°C, Vlogic = +5V, unless otherwise specified