MP3312 datasheet(10/15 Pages) MPS

10 / 15 page

MP3312 － 2.7V-5.5V INPUT, 38V OVP, DUAL-CHANNEL WHITE LED DRIVER

MP3312 Rev. 1.02

www.MonolithicPower.com

1/13/2015

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

Figure 2—1-wire command structure

1-wire interface defines logic 0 and logic 1 by

comparing the time of the signal low level and

high level, 1 cycle means 1 logic bit. The bit

detection starts with a falling edge on the EN

pin and ends with the next falling edge. Shown

as Figure 3

Low logic (logic 0): tLOW≥3* tHIGH

High logic (logic 1): tHIGH≥3* tLOW

Figure 3—1-Wire Bit Definition

The EN pin needs to distinguish EN signal and

digital dimming signal when set up boost driver.

Chip only receives 1-wire signal when EN pin

signal matches 1-wire protocol during 1ms 1-

wire

detection

window.

1-wire

dimming

sequence is described as below, and shown in

Figure 4.

1. Pulling VIN and PWM to high.

2. Pulling data line from low to high for tDELAY (1-

wire detection delay time, 100us) and this

rising edge is the start of 1-wire detection

window.

3. After 1-wire detection delay time, pulling data

line to low for more than tDETECTION (1-wire

detection time, 260us). Then pulling data

line to high.

4. The sum of 1-wire detection delay time and

1-wire detection time should be less than tWIN.

(The time of 1-wire detection window,1ms).

Figure 4—1-Wire Dimming Sequence

MP3312 데이터시트(PDF) 10 Page - Monolithic Power Systems